Rambus Unveils SOCAMM2 Chipset for Next-Generation AI Server Memory

Rambus Inc. (NASDAQ: RMBS), a leading provider of chip and silicon IP solutions, has introduced its new SOCAMM2 (Small Outline Compression Attached Memory Module) chipset. This innovative chipset is engineered to enable low-power, high-performance LPDDR5X-based memory modules, specifically designed for the demanding requirements of AI server platforms. The SOCAMM2 chipset marks the initial phase of Rambus’ broader roadmap for LPDDR-based server module solutions, underscoring the company’s commitment to advancing memory architectures in collaboration with industry partners. This launch further expands Rambus’ comprehensive portfolio of memory interface chipsets, supporting all JEDEC-standard DDR5 and LPDDR5 memory modules.

Addressing the Evolving Needs of AI Data Centers

The rapid growth and diversification of AI-driven data center workloads are fundamentally transforming system requirements. Modern AI applications demand solutions that optimize power efficiency, scalability, and form factor, while delivering robust performance. SOCAMM2 memory modules, leveraging LPDDR technology, offer a forward-thinking architectural approach to these challenges. By combining high performance with reduced power consumption in a modular and serviceable form factor, SOCAMM2 modules are poised to meet the evolving needs of AI infrastructure.

The Rambus SOCAMM2 chipset is purpose-built to support this transition. It delivers essential control, telemetry, and power delivery functions required by JEDEC-standard SOCAMM2 memory modules, ensuring reliable operation in high-performance AI server environments.

Industry Collaboration and Ecosystem Support

Industry leaders recognize the significance of SOCAMM2 in shaping the future of AI server memory. Rami Sethi, SVP and general manager of Memory Interface Chips at Rambus, emphasized the critical role of memory in enabling performance, efficiency, and scalability for AI systems. He noted that SOCAMM2 is the first in a planned family of LPDDR-based server module chips, with ongoing development aimed at supporting future AI infrastructure.

Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron, highlighted the importance of a robust ecosystem around LPDDR-class server memory as AI continues to push the boundaries of compute performance and power efficiency. He welcomed Rambus’ commitment to SOCAMM2 and its integrated chipset offering, which supports the evolution of next-generation AI system designs.

Soo Kyoum Kim, associate VP of memory semiconductors at IDC, pointed out that memory architectures like SOCAMM2 are essential for balancing performance and efficiency as AI workloads challenge data center power, bandwidth, and density limits. He stressed the value of contributions from ecosystem members such as Rambus in enabling the adoption of LPDDR-based memory in AI servers.

Key Features of the Rambus SOCAMM2 Chipset

SOCAMM2 technology replaces traditional soldered LPDDR memory with detachable, upgradable modules. This approach combines the efficiency of LPDDR memory with the serviceability required in data center environments. The Rambus LPDDR5X SOCAMM2 chipset supports reliable, power-efficient operation of LPDDR-based server memory modules at speeds up to 9.6 Gb/s. Key features include:

  • SPD Hub for module identification, configuration, and telemetry
  • 12-amp (A) and 3 A voltage regulators for localized, efficient power conversion