TSMC Achieves Breakthrough in Advanced Chip Packaging Yields
TSMC has reached a significant milestone in semiconductor manufacturing, achieving near-perfect yields with its latest CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology. The company now reports a baseline yield of approximately 98% for its current CoWoS process, a notable accomplishment for a technology that only recently entered mass production.
CoWoS enables the integration of a die area up to 5.5 times the reticle limit, translating to about 858 mm² per die. This advancement allows for the packaging of up to 4,720 mm² of silicon on a single CoWoS-L package, with only 1-2% of packaged designs encountering issues. This high yield rate is particularly impressive given the complexity and scale of the designs now being produced.
Scaling Up: Preparing for Even Larger Chip Designs
Looking ahead, TSMC is preparing to support even larger chip designs. The company is developing packaging solutions for dies up to 14 times the reticle size, which equates to a massive 12,012 mm² of silicon on a single package. This next-generation packaging technology is expected to be available by 2029, coinciding with the mass production of TSMC’s A13 process node.
As chip sizes increase, so do the engineering challenges. Designs that exceed three times the reticle limit must be carefully managed to prevent thermal warping and mechanical stress. TSMC continues to collaborate closely with its customers to address these challenges, ensuring reliable performance and manufacturability at scale.
Advancements in Hybrid Bonding with SoIC Technology
In addition to CoWoS, TSMC is making significant progress with its SoIC (System on Integrated Chips) hybrid bonding technology. The SoIC process, which achieved a 6-micron hybrid bonding pitch in high-volume production last year, is on track to reach a 4.5-micron pitch by 2029. This advancement will enable the stacking of A14 chips, further increasing integration density.
SoIC technology offers substantial benefits, delivering over 50 times the interconnect density and five times the energy efficiency compared to conventional packaging methods. These improvements position SoIC as a leading alternative in TSMC’s advanced packaging portfolio, supporting the growing demand for high-performance, energy-efficient semiconductor solutions.
TSMC’s ongoing innovations in advanced packaging and hybrid bonding reinforce its leadership in the semiconductor industry, consistently meeting production timelines and maintaining strong customer satisfaction.
