NVIDIA Prepares Next-Generation "Feynman" GPUs on TSMC’s Advanced A16 Node
NVIDIA is already moving forward with the development of its next-generation GPU microarchitecture, codenamed "Feynman," according to supply chain sources and insiders close to TSMC. This new architecture is set to succeed the upcoming "Rubin" and "Rubin Ultra" GPUs, marking a significant leap in graphics processing technology.
Transition to TSMC’s 1.6 nm A16 Node
In a strategic shift, NVIDIA has chosen to bypass TSMC’s N2 family of nodes, opting instead for the more advanced A16 process technology. The A16 node, built on a 1.6 nm process, is expected to deliver substantial improvements in performance and efficiency. Mass production of the "Feynman" GPUs is scheduled for the second half of 2028, positioning NVIDIA at the forefront of semiconductor innovation.
Advanced Packaging and Power Delivery Technologies
The "Feynman" GPUs will leverage TSMC’s latest advancements in backside power delivery, a feature of the A16 node that enhances power efficiency and thermal management. NVIDIA is also set to utilize cutting-edge packaging technologies, including 3D chiplet integration with SoIC (System on Integrated Chips), CoWoS-L 2.5D packaging, and next-generation panel-level packaging.
Initially, NVIDIA will employ SoIC 3D stacking to combine multiple chiplets within a single package. This approach reduces the distance data must travel between chips, minimizing latency and boosting overall performance. These 3D-stacked chips will then be arranged side-by-side using CoWoS-L or CoPoS packaging, resulting in a multi-kilowatt GPU design capable of delivering processing power measured in dozens of PetaFLOPS.
Customized HBM Memory and Enhanced Data Processing
For memory, NVIDIA is collaborating with partners to develop customized High Bandwidth Memory (HBM), likely HBM4E, tailored for the "Feynman" architecture. This next-generation memory will feature a specialized base die that can integrate logic elements such as memory controllers or packet processing units. By enabling data pre-processing before it enters memory, this innovation aims to further reduce latency and accelerate data throughput, depending on NVIDIA’s specific implementation goals.
Co-Packaged Optics: Breaking the Bandwidth Barrier
A key innovation in the "Feynman" GPUs will be the introduction of co-packaged optics (CPO). By integrating optical interconnects directly between GPUs, NVIDIA aims to overcome the limitations of traditional copper connections, significantly reducing both latency and power consumption. For context, the current "Blackwell" NVL72 rack achieves a total bandwidth of 130 TB/s between GPUs. The upcoming "Rubin" architecture is expected to double this to 260 TB/s, with "Rubin Ultra" reaching 520 TB/s. With "Feynman," NVIDIA is targeting a breakthrough of over 1,000 TB/s in total system bandwidth, entering the petabyte-per-second range.
This leap in bandwidth will be made possible through TSMC’s COUPE technology, enabling the high-speed, low-latency optical connections required for next-generation AI and high-performance computing workloads.
As NVIDIA continues to push the boundaries of GPU technology, the "Feynman" architecture represents a major step forward in performance, efficiency, and system integration, setting new standards for the future of computing.
