NVIDIA Unveils NVHBM: A New Era of High-Bandwidth Memory for GPUs and XPUs
NVIDIA has introduced NVHBM, a custom high-bandwidth memory (HBM) technology designed to enhance GPU and XPU performance by rethinking how memory controllers are integrated. Unlike traditional HBM, which places the memory controller on the compute die, NVHBM relocates the controller into the HBM base die itself. This architectural shift is set to deliver significant improvements in memory bandwidth, power efficiency, and compute die utilization for future NVIDIA GPUs and third-party XPU customers via NVLink Fusion.
Key Advantages of NVHBM Over Standard HBM4E
The primary innovation behind NVHBM is the move of the memory controller from the compute die to the 3D HBM stack. In standard HBM designs, the memory controller occupies valuable silicon area on the compute die, limiting the space available for compute logic. By integrating the controller into the HBM base die, NVHBM frees up this area, allowing for more compute resources and improved overall efficiency.
According to NVIDIA, NVHBM offers up to 30% higher memory bandwidth, 15% lower HBM power consumption, and up to 25% more usable compute die area compared to standard HBM4E. These gains are achieved through a redesigned physical memory interface. While standard HBM relies on wide interface connections that increase the package footprint, NVHBM’s custom PHY reduces the I/O area by as much as 67% compared to JEDEC HBM4E. This narrower interface also simplifies interposer routing, unlocking up to 80% more usable silicon across the chip layout.
The reduced PHY footprint not only saves space but also eases routing constraints on the interposer. This is particularly important when integrating multiple HBM stacks alongside a large compute die, as it allows for more flexible and efficient chip designs.
Power Efficiency and Data Center Impact
NVHBM’s 15% reduction in HBM power consumption is more than just an efficiency improvement—it provides additional thermal headroom for the compute die. This is especially valuable in enterprise and data center environments, where thousands of compute units operate simultaneously. NVIDIA highlights that in a 1-gigawatt data center using 2,000 W XPUs, the power savings from NVHBM could enable up to 15,000 additional XPUs within the same power envelope, significantly boosting compute capacity.
Industry Momentum and Future Prospects
The high-bandwidth memory landscape is advancing rapidly. At Hot Chips 2026, Samsung announced its upcoming HBM4E memory, capable of 16 Gbps per pin—up from the current 14 Gbps—delivering up to 4 TB/s per stack across 2,048 pins. When combined with the 30% bandwidth improvement claimed by NVIDIA for NVHBM, a single NVHBM stack could theoretically achieve around 5.2 TB/s, setting a new benchmark for memory performance in high-end computing.
NVIDIA has also confirmed that NVHBM will be validated across multiple memory vendors, streamlining supplier qualification for customers. Amazon’s Annapurna Labs is the first announced partner to collaborate on NVHBM, signaling strong industry support for this next-generation memory technology.
With NVHBM, NVIDIA is poised to redefine the standards for high-bandwidth memory in GPUs and XPUs, offering substantial gains in bandwidth, efficiency, and scalability for data centers and enterprise computing.
