Samsung Unveils Next-Generation Memory Roadmap at SEMICON Taiwan 2026
At SEMICON Taiwan 2026, Samsung revealed its latest advancements in memory technology, highlighting the upcoming HBM5 and zHBM architectures. These innovations set new benchmarks for performance, efficiency, and thermal management, signaling Samsung’s commitment to leading the memory industry into the next era.
HBM5: Doubling Performance and Enhancing Efficiency
Samsung’s HBM5 memory is designed to deliver twice the performance of its predecessor, HBM4E, while achieving a 20% improvement in performance per watt. Additionally, HBM5 reduces thermal resistance by 20%, addressing the growing demand for efficient cooling in high-performance computing environments.
The technological leap is driven by a transition from the 4 nm process used in HBM4 and HBM4E to Samsung’s advanced in-house 2 nm node. HBM5 will also offer expanded stack options, supporting 12, 16, and 20 layers to accommodate diverse application requirements. Mass production of HBM5 is projected to begin around 2028.
In parallel, Samsung confirmed at the Hot Chips 2026 conference that it is preparing to ship HBM4E memory with speeds of 16 Gbps per pin, a significant increase over the current HBM4, which operates at 11.7 Gbps per pin.
zHBM: Redefining High Bandwidth Memory Architecture
Samsung’s zHBM architecture introduces a transformative approach by stacking memory directly on top of the processor, rather than placing it beside the accelerator as in conventional HBM designs. This vertical integration shortens the data path, resulting in higher bandwidth and improved efficiency.
With zHBM, Samsung aims for an eightfold increase in raw performance and a threefold boost in performance per watt compared to HBM4E. Thermal resistance is expected to decrease by 75-90%, addressing one of the most critical challenges in high-density memory solutions. The first concept models of zHBM were showcased at FMS 2026, with commercial launch anticipated after 2029.
The industry is witnessing a broader shift in HBM architecture. For example, NVIDIA recently introduced its NVHBM custom memory, which relocates the memory controller into the HBM base die, further optimizing data flow and efficiency.
Advancements in NAND: Introducing zNAND-O
On the NAND front, Samsung is developing zNAND-O, with sampling targeted for 2028. This next-generation NAND technology is engineered to deliver ten times the bit density of DRAM and seven times the read bandwidth, all while maintaining the power efficiency of conventional NAND solutions. The competitive landscape is intensifying, as China’s YMTC has announced its ambition to surpass both Samsung and SK hynix by the end of 2027.
The C.U.B.E Framework: Guiding Future Memory Innovation
Samsung also introduced its "C.U.B.E" framework at the Memory Executive Summit, outlining four strategic priorities: Capacity, Utilization, Bandwidth, and Efficiency. The framework emphasizes vertical memory expansion to increase capacity without enlarging the PCB footprint, optimized 3D architectures to minimize latency, vertical high-speed channels to replace traditional horizontal data paths, and a strong focus on power efficiency and thermal management at the bit level.
With these advancements, Samsung is positioning itself at the forefront of memory innovation, addressing the evolving needs of data-intensive applications and setting the stage for the next generation of computing.
