Quintauris GmbH Established to Advance RISC-V Adoption

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP Semiconductors, and Qualcomm Technologies, Inc., have officially formed Quintauris GmbH. The company, headquartered in Munich, Germany, aims to promote the global adoption of RISC-V by facilitating next-generation hardware development.

The establishment of Quintauris was announced in August, with the goal of becoming a single source for compatible RISC-V-based products, providing reference architectures, and promoting widely-used solutions across various industries. Initially, the focus will be on the automotive sector, but there are plans to expand to include mobile and IoT applications. Alexander Kocher has been appointed as the CEO of Quintauris. Kocher brings extensive experience, having previously served as President and CEO of Elektrobit, a global supplier of embedded and connected software products for the automotive industry. Before joining Elektrobit, Kocher held the position of Vice President and General Manager of Wind River's automotive business unit.

"This is a very exciting opportunity for Quintauris and the industries we will serve," said Alexander Kocher, CEO of Quintauris. "We will bring game-changing innovation and scalability to the next generation of hardware development, with a focus on combining the best elements of RISC-V in a unified, commercialized proposition. We are fortunate to have the support of established players in the semiconductor industry, which demonstrates our ambition for Quintauris to be a long-term, sustainable offering. We strongly believe in the power of collaboration with the RISC-V community, and as we continue to grow our company, we look forward to engaging with the ecosystem to accelerate development and enhance the resilience of the broader semiconductor industry."

All necessary regulatory approvals have been obtained, and Quintauris was officially established on December 22, 2023.

RISC-V is an open-source chip architecture based on "Reduced Instruction Set Computer" (RISC) principles. It was originally developed by researchers at the University of California, Berkeley in 2010. For more information on RISC-V, please visit: https://riscv.org/about/.